Practical Examples of PSL Usage
Aldec will be presenting a seminar at 11am (Pacific Daylight Time) on Thursday, July 17, 2008. Previous presentation in this thread ("Understanding Assertions - The Key to Efficient Usage") provided solid theoretical background for PSL usage in hardware design and verification. Using this background, current presentation shows how to use PSL in real life designs to make verification more efficient.
Agenda
- Clocking PSL properties
- Popular property patterns
- Properties in assertions and functional coverage
- PSL examples for typical design units
- Common coding mistakes
- Methods of binding verification units to design units
- PSL embedded in the HDL code vs. saved in separate files
More info: Advanced Verification Methodology Seminars
If you found this page useful, bookmark and share it on:
Possibly of Interest
- Training: SystemVerilog Assertions and Functional Coverage
- SystemVerilog Assertions and Functional Coverage
- System Verilog Assertions Training
- SystemVerilog Assertions – Methodology and Language Overview Webinar
- Enhanced Open Verification Methodology
EDA Blog Newsletter
Don't have time to visit EDA Blog everyday? Then sign up for our free newsletter. We'll send you an email when we have something to share with you. Your email address will be kept confidential and we will not share, sell, or rent it to anyone. You can unsubscribe at any time by clicking a link in the email.
If you are familiar with RSS feeds, you can also sign up for our free blog feed. Our RSS feed is updated in real-time while our newsletter is updated daily.
