Synopsys, Inc. (NASDAQ: SNPS) recently announced the DesignWare PHY IP for PCI Express 2.0 (Gen II), based on the PCI Express 2.0 base specification. The DesignWare PHY IP for PCI Express 2.0 is available in leading 65 nm foundry processes such as the Common Platform technology from IBM and Chartered, which provides users with a unique “copy exact”, multi-source capability enabling them to use multiple foundries with no design re-work. The DesignWare IP digital controllers and verification IP for PCI Express 2.0 are also available today.
PCI Express 2.0 doubles the 1.1 specification transfer speed from 2.5 Gbps to 5.0 Gbps per lane, meeting the demand for both increased bandwidth and narrower interconnect links in data center, storage, high-end graphics and networking infrastructure applications. Backwards compatibility with the PCI Express 1.1 and PIPE specifications, allows designers to optimize performance and power while maintaining interoperability with existing devices. The DesignWare PHY IP substantially exceeds the PCI Express 2.0 electrical specification in areas such as jitter, margin and receive sensitivity, thus delivering a robust design without sacrificing performance. The DesignWare PHY IP for PCI Express 2.0 includes advanced built-in diagnostic capabilities and ATE test vectors enabling at-speed production testing of the PHY. It is implemented in standard CMOS digital technologies and does not require special process options, providing both ease of integration into a SoC, and ensuring high production yields.
More info: Synopsys DesignWare PCI Express Solutions