eASIC Corporation is holding a $30,000 placement design challenge. This challenge is designed to inspire innovation in the area of placement algorithms. eASIC will offer a total prize of $30,000 to the individuals or groups that can implement the most efficient placement algorithms. Eligible design challenge contestants can submit proposals either as teams or as individuals. To facilitate this design challenge, eASIC will provide design examples, utilities for evaluation, and representations of its unique architecture.
eASIC’s zero mask-charge, Nextreme ASIC devices provide designers with ASIC like cost and power consumption with the design simplicity and fast turnaround of FPGAs. Nextreme is built on a configurable fabric which combines Look-Up-Table (LUT) based cells with single via-layer customized interconnect. eASIC’s and its EDA partners have developed design software tools that exploit the advantages of eASIC’s Nextreme devices. However, eASIC’s mission is to continue to inspire innovation and aggressively transition it’s software from being world-class to “best in class.” To accelerate this aggressive effort, eASIC is introducing a challenge to academia.
The challenge to academia is simple: Can you implement placement better than eASIC’s engineers and it’s partners? The eASIC’s design challenge will be limited in scope is to the area of placement algorithms and methodologies in order to keep it manageable. eASIC invites all comers, including individuals and institutions to take on its Placement Design Challenge.
A total of $30,000 will be awarded to the wining institutions, groups or individuals. The contest winners will be determined by quantitative measurements on their submitted solutions including total wire-length and congestion characteristics.
More info: Register for Placement Design Challenge