Guest Post by:
45th DAC Executive Committee
The Design Automation Conference (DAC), to be held in Anaheim from June 8th – 13th, provides an ideal platform to deliver several educational opportunities for all attendees. The hands-on tutorials is one such unique opportunity. One or more exhibitors participate jointly in designing a practical session that demonstrates the value of their offering. The exhibitors focus on detailing how their tools and methodologies solve a particular design problem by using live product demonstrations and hands-on experience. It is an ideal opportunity to meet colleagues who are tackling similar problems and share thoughts and ideas.
Each year, the hands-on tutorials are organized around a theme. The theme is selected in early November. Several factors influence the decision of a theme, such as relevance of the topic to the attendees and the number of exhibitors who can collaborate and organize tutorials supporting the theme. Proposals are solicited from all exhibitors shortly thereafter. The final proposals are selected after a careful review based on the content and applicability of the proposal to the theme. We encourage multiple vendors to collaborate on a single tutorial. Previous themes include “Design for Manufacturing” (2007) and “Low Power Design” (2006).
Consistent with focus on chip design and the increasing use of intellectual property (IP), the theme this year is “Embedding IP in your design: challenges and solutions”. We have four hands-on tutorials spread over the conference days. Each tutorial lasts three hours. The topics range from IP verification, selection, integration, validation and test. For DAC 2008, several companies have come together to put together the tutorials; the primary organizers are Certess Inc., Denali, Synopsys Inc. and Apache Design Solutions. A brief summary of the Hands-On Tutorials is included below:
Elevating confidence in design IP through mutation based analysis technology
This hands-on tutorial from Certess Inc. includes STMicroelectronics and Brian Bailey Consulting as co-participants. They will focus on reuse of intellectual property and the critical challenge of verification in an SOC. Participants will gain hands-on experience in setting up Certitude for an existing verification environment, analyzing specific verification weaknesses, and improving the verification strategy.
Hardened DDR PHY Integration
Denali Software Inc. and SiSoft come together to highlight the issues involved with integrating a DDR hardened PHY into a complete system, which includes the package and board.
Advanced methodologies for validating and integrating high speed serial interconnects in the ultra deep sub-micron CMOS era
Synopsys Inc. and OpenSilicon collaborate to discuss integration, verification and validation issues involved with integrating high speed intellectual property on a design.
IP Validation for macro & embedded SOC
Apache Design Solutions will present an accurate power and noise analysis flow based on Apache’s RedHawk platform. It enables designers to verify the power integrity of IPs at the block-level and creates a comprehensive model of varying levels of complexity for SoC-level analysis.
I encourage design engineers and design managers to strongly consider attending DAC for a wide multiplicity of offerings at the conference such as a lively exhibition floor, exciting keynotes and a highly relevant technical program. The details of the conference, including the hands-on tutorial information, can be found on the DAC website. And while you are there, I urge you to register for a hands-on tutorial.