At DAC, Calypto Design Systems Inc. will give free copies of PowerPro-filer on a one gigabyte memory stick. PowerPro-filer is a utility that calculates Clock-Gating Efficiency and the percentage of registers clock gated in an RTL design block. PowerPro-filer is a Linux program that reads synthesizable Verilog RTL activity vector file (SAIF or VCD) and reports how well a register transfer level (RTL) design is optimized for power by providing designers with Clock-Gating Efficiency statistics. Clock-gating Efficiency correlates directly to how well a designer’s clock gating implementation impacts dynamic power.
During the Design Automation Conference, Calypto will demonstrate how toy reduce power and improve design quality using PowerPro[tm] CG (clock gating) for automated RTL power optimization and SLEC[tm] (Sequential Logic Equivalence Checker) for functional verification. Calypto will also participate in the following sessions:
- Keeping Hot Chips Cool: Are IC Thermal Problems Hot Air?
Devadas Varma, chairman and founder
Wednesday, June 11, from 4:30-6 p.m. in room 210CD
- Formal Verification, Dude or Dud? Experience from the Trenches
Anmol Mathur, chief technology officer and founder
Thursday, June 12, from 2- 4 p.m. in room 207.
- Leveraging Sequential Equivalence Checking to Enable System-level to RTL Flows
Pascal Urard, STMicroelectronics
- Construction of Concrete Verification Models from C++
Malay Haldar, senior engineering manager
Thursday, June 12, from 4:30-6 p.m. in room 208AB.
More info: Calypto at DAC