Aldec ALINT Verilog Design Rule Checker
ALINT, from Aldec Inc., is a stand-alone Verilog design rule checker. ALINT complies with the second edition of the STARC "RTL Design Style Guide for Verilog HDL." ALINT reduces the risk of developing complex multi-million gate ASICs by resolving structural, coding and consistency problems early in the design cycle. It detects design issues at the point of creation. ALINT offers a comprehensive solution for clock & reset analysis, detecting potential clock domain crossing (CDC) issues. ALINT is available today and includes an HDL Editor, STARC based design rules, and lint engine.
ALINT Features
- Verilog® Code checks, design elaboration and synthesis emulation
- Clock Domain Crossing (CDC)
- User Modified Design Rules
- Fast analysis of complex ASIC/FPGA-SOC designs
- Cross-probing of Error messages to source code
- Configuration Manager
- Supports STARC Design Rules
ALINT is a static Verilog design rule checker that includes support for rules that operate at several levels of abstraction:
- Verilog Language
Verilog Language Rules enable detection of errors related to the use of undesired data types, bit-width mismatches, missing size/base specification for constants and parameters. These rules also detect typical errors with logic designs including bitwise and conditional expressions, style, and naming conventions. - Synthesizable Verilog RTL Subset
Synthesizable Verilog RTL Subset Rules are automatically applied to the Verilog code and ALINT performs checks against the use of improper constructs for synthesis: unspecified conditional statements, resource sharing in the synthesized netlist, simulation/synthesis mismatches and inaccuracy with multiple assignments to the same signal. - Block-Level Netlist
Built-in synthesis emulation automatically recognizes typical hardware elements from RTL code and builds a internal netlist model that allows detection of unwanted latches, flip-flops with fixed values on the inputs, detection of problems with asynchronous controls of inferred flip-flops and issues with multiply-driven nets. - Chip-Level Netlist
Chip-Level Netlist Rules monitor a typical DFT problem, such as influence of global clock signals on non-clock ports, uncontrollability of clock/reset/enable pins of storage elements, unwanted asynchronous feedbacks and interconnections typically leading to DFT and ATPG tools malfunctions.
ALINT stores all violations to a highly optimized database and then displays all violations in the console window. Double-clicking on the violation reported in the console window cross-probes directly to the line of Verilog source code creating the violation. Post-linting analysis can be performed on any violations stored in the database, eliminating the need to run ALINT again in order to recall violations collected in other parts of a project.
The ALINT engine provides a flexible configuration mechanism. ALINT provides a preinstalled set of STARC rules. Rules can be combined together in different ways to form rule sets and policies that are treated by ALINT as a single object. The rule, rule set and policy properties can be easily configured, providing additional flexibility in design analysis.
More info: Aldec ALINT | STARC
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