The IC Compiler 2007.12 release, from Synopsys, Inc. (NASDAQ: SNPS), features the industry’s first concurrent hierarchical design system. As designers migrate to smaller geometries, on-chip integration increases and design sizes mushroom, making hierarchical design almost mandatory. Current-generation design tools rely on a “plan-then-implement” flow which begins to break down in the face of these large designs, which often include multiple modes and multiple voltage domains. The IC Compiler 2007.12 release transcends these flows by enabling a concurrent methodology where planning occurs in tandem with implementation, delivering faster time to tapeout. The 2007.12 release also introduces new advances in clock tree synthesis technology that improves clock skew and lowers power dissipation. The new release directly boosts designer productivity by providing a 30 percent reduction in total run time.
Historically, “plan-then-implement” flows have worked well for simple designs. However, for complex designs, these flows lead to late discovery of physical design issues, resulting in overdesign and often requiring iterations back to the early planning stages. For these complex designs, a concurrent flow that seamlessly blends planning and implementation tasks and offers an integrated environment with a single timer and high correlation with sign-off becomes increasingly critical. IC Compiler 2007.12 provides hand-craft-quality macro placement, intelligent power network support, and MinChip technology for automatic die-size reduction, all on a single timer foundation that enables faster time to closure with higher quality of results (QoR). This flow is differentiated by a high degree of automation combined with high-quality optimization.
Prominent among core-technology advances in the 2007.12 release are optimization improvements which maintain IC Compiler’s QoR advantage while slashing total runtime by 30 percent, as validated across a broad range of 65-nanometer (nm) customer designs. IC Compiler 2007.12 introduces unique advances in clock tree synthesis, such as an innovative new clustering algorithm which delivers 20 percent reduction in clock buffering area to improve routing congestion as well as power dissipation. In addition, new skew optimization enables improved timing closure for challenging designs, and an integrated clock-gate merging capability delivers another five to ten percent reduction in clock tree power.
More info: Synopsys