Titan(tm), from Magma® Design Automation Inc. (Nasdaq: LAVA), is the first full-chip mixed-signal design, analysis, and verification platform. Unlike other design solutions, Titan tightly integrates mixed-signal implementation with digital implementation, circuit simulation, transistor-level extraction, and verification. Titan Chip Finishing will be the first product to be released on this platform and is available now.
Because Titan is based on Magma’s unified data model, it works seamlessly with Magma’s Talus® digital IC implementation, FineSim(tm) circuit simulation, QuickCap® TLx transistor-level extraction and Quartz DRC and Quartz LVS physical verification products. As a result, analog and digital design teams are no longer isolated and can have clear visibility into their counterparts’ design space.
Today, analog design flows and teams are isolated from the digital world. Analog integrated circuits are still largely full-custom and are painstakingly crafted by hand. In addition to being time-consuming and prone to error, this transistor-level design style does not allow an existing design to be easily transferred to a new foundry or process/technology node. Instead, the migration of such a design effectively requires the circuit to be re-implemented from the ground up. With Titan, analog designers will still apply their expertise in defining the first circuit topology, but porting to new nodes will be significantly easier.
In traditional flows, chip finishing – the point at which the digital and analog blocks of a design are placed and routed together – is a time-consuming and manual task. Titan Chip Finishing provides complete and automated chip finishing capabilities. This fast, high-capacity system integrates mixed-signal layout with the Talus place-and-route capabilities. It can manipulate the largest designs with ease, automates analog and special net routing through an efficient constraints-based approach and makes all mixed-signal layout changes immediately available for physical and timing verification sign-off analysis through a live interface with Talus, Quartz DRC and Quartz LVS. Titan Chip Finishing can implement late engineering change orders (ECOs) that affect both analog and standard-cell components without significantly delaying the schedule.
Titan offers an integrated simulation environment using the industry’s leading circuit simulator, FineSim, along with the gold standard tool for parasitic extraction, QuickCap TLx. When coupled with ground-breaking schematic driven layout, analog circuit optimization, and analog placement-and-routing, Titan provides a level of efficiency in the analog design domain that is similar to that of the digital domain. For true mixed-signal design, the FineSim interface also allows for full-chip circuit simulation, offering SPICE-level accuracy for the analog portions of the design and fast SPICE-level accuracy for the digital portions of the design. This ensures that the analog/digital interfaces are well simulated and verified before committing the chip to silicon.
More info: Magma Design Automation