Tanner EDA recently announced HiPer PX and Verilog-A. Both are now part of Tanner Tools V13.0. HiPer PX reduces design errors and shortens the design verification process by generating highly accurate RC models for interconnect parasitics that include higher-order moments and are guaranteed to be accurate up to a user-defined signal frequency. HiPer PX is an advanced parasitic extraction tool targeted for analog, mixed-signal and RF integrated circuits.
HiPer PX is fully integrated within L-Edit, ensuring ease of use and minimal training time. It is available in two variants: HiPer PX2D extracts parasitics using a highly efficient boundary element estimation of parasitics, and HiPer PX3D which uses a highly accurate 3D finite-element method to extract vertical and lateral coupling capacitances. As a superset, HiPer PX3D includes all the capabilities of HiPer PX2D, and is capable of operating in either mode.
T-Spice now incorporates a full Verilog-A implementation, enabling designers to easily and quickly write their own custom behavioral models for early system level simulations. Verilog-A enables the designer to do system level analog simulations much earlier in the design process. Verilog-A is featured as a cost option for the T-Spice simulator, and is included with Tanner’s HiPer Simulation and HiPer Silicon packages.
More info: Tanner EDA