Synopsys, Inc. (NASDAQ: SNPS) and Semiconductor Manufacturing International Corporation (SMIC) (NYSE: SMI)(SEHK: 0981.HK) recently released an enhanced 90 nanometer (nm) hierarchical, multi-voltage RTL-to-GDSII reference design flow that benefits from advanced synthesis, design-for-test (DFT) and design-for-manufacturing (DFM) capabilities. Key features of the reference flow include topographical synthesis in the Design Compiler(tm) Ultra product, scan compression in the DFT MAX product and critical area analysis in the IC Compiler place-and-route product. Together these capabilities help to lower the cost of implementing and testing systems-on-a-chip (SoCs). Reference Design Flow 3.2 is available now.
The enhanced reference design flow 3.2, based on SMIC’s 90-nm low-leakage process and Synopsys’ Pilot Design Environment, has been validated on Synopsys’ Galaxy(tm) Design Platform with the ARM® low power design kit developed for SMIC’s 90-nm process. The reference flow uses Design Compiler Ultra topographical technology to accurately predict post-layout timing, power and area during synthesis, thereby reducing costly design iterations between synthesis and layout.
Advanced capabilities for low power design include insertion and placement optimization of isolation cells, creation of multiple voltage areas and power meshes, and synthesis of multiple voltage-aware clock trees. To help reduce standby leakage, the design flow utilizes power gating techniques that shut off areas of the chip when they are not needed for a function. DFT MAX synthesizes scan compression circuits that substantially lower costs by decreasing the amount of data and time required for manufacturing test. The tool reduces the number of scan chain connections that cross voltage domains, lowering the area impact of DFT by reducing the number of required level shifters and isolation cells. Other DFM capabilities in the flow include via optimization and wire spreading and antenna fixing with Hercules runset.