Low Power Coalition’s Common Power Format Roadmap
Silicon Integration Initiative (Si2) recently published the Low Power Coalition’s (LPC) roadmap for Common Power Format (CPF) extensions planned out through mid-2009. Si2 is an organization of industry-leading semiconductor, systems, EDA, and manufacturing companies focused on improving the way integrated circuits are designed and manufactured in order to speed time to market, reduce costs, and meet the challenges of sub-micron design. The Low-Power Coalition (LPC) is responsible for delivering enhanced capabilities in low-power Integrated Circuit (IC) design flows in particular relating to specifications of low-power design intent, architectural tradeoffs, logical/physical implementation, design verification and testability.
The announced CPF extensions cover the following items:
Immediate – Requirements for CPF Version 1.1 (target release – mid 2008)
- Hierarchical flow support
- Memory modeling styles and support
- Gate-level verification flow CPF support
- Power estimation support
- Clocking and related updates required to drive power optimization
Medium Term – Requirements for CPF 1.2 (target release – early 2009)
- Pre-Si and post_Si power modeling and budgeting
- Test power definitions not represented in CPF
- Investigate Load_foreign
- IO modeling and representation
Long Term – Requirements for CPF 2.0 (target release – mid 2009)
- CPF to drive debug related to power
- CPF based system level definition
More info: Si2 Power Format Requirements (pdf)
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