Cadence Design Systems, Inc. (NASDAQ: CDNS) and Mentor Graphics Corp. (NASDAQ: MENT) recently enhanced the source-code library and user documentation for the Open Verification Methodology (OVM), the industry’s first open, interoperable SystemVerilog verification methodology. The enhancements are the result of feedback from the growing user community. Distributed under the standard open-source Apache(tm) 2.0 license, the OVM source code, usage examples, and documentation may be downloaded free of charge from OVM World.
The Open Verification Methodology, based on IEEE Std. 1800(tm)-2005 SystemVerilog standard, is the first open, language-interoperable, SystemVerilog verification methodology in the industry. It provides a methodology and accompanying library that allow users to create modular, reusable verification environments in which components communicate with each other via standard transaction-level modeling interfaces. It also enables intra- and inter-company reuse through a common methodology and classes for virtual sequences and block-to-system reuse, and full integration with other languages commonly used in production flows.