Cadence ARM11, ARM1176JZF-S Reference Methodologies
Cadence Design Systems, Inc. (NASDAQ: CDNS) and ARM [(LSE: ARM); (NASDAQ: ARMHY) created implementation reference methodologies for the ARM11(TM) MPCore(TM) multicore processor and the ARM1176JZF-S(TM) processor. The Cadence reference methodologies for the two ARM processors provide enhanced design solutions for designing multicore, low-power devices.
The reference methodology for the ARM11 MPCore multicore processor provides a high-performance reference flow that offers predictable, low-risk implementation of multiprocessor configurations. Both the ARM11 MPCore processor and low-power ARM1176JZF-S processor flows have been pre-validated with ARM Artisan® Physical IP in order to optimize the implementation of ARM synthesizable processor IP.
The low-power reference methodology for the ARM1176JZF-S processor provides enhanced features required to support IEM technology, which has been shown to reduce CPU energy consumption by more than 60%, and supports the Dynamic Voltage and Frequency Scaling (DVFS) hardware technique that IEM technology exploits.
The reference methodologies feature the Common Power Format (CPF), which enables the up-front specification of power domains, power modes, level shifting and isolation rules to automate advanced low-power design techniques. The methodologies leverage a wide range of products of the Cadence® Low-Power Solution, including the Cadence SoC Encounter(TM) RTL-to-GDSII system, Encounter® RTL Compiler with global synthesis, Encounter Conformal® Low Power, and VoltageStorm® power rail analysis.
The jointly developed reference methodologies offer significant benefits in multiprocessing and power consumption for designing the next-generation consumer devices, which require performance and superior power management. The reference methodologies help reduce time to tapeout of customized designs, thereby gaining considerable time-to-market and cost benefits.
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