Seminar: Accelerating Silicon Success with Silicon Aware IP
Virage Logic Corporation (NASDAQ:VIRL) and TSMC are offering a free technical lunchinar and demonstration entitled, Accelerating Silicon Success with Silicon Aware IP for Yield Acceleration & Time-to-Volume. The seminar and demonstration will focus on bridging the gap between design and manufacturing and will highlight the STAR(TM) Memory System with the new STAR(TM) Yield Accelerator option for advanced design and process technology challenges. The event will take place on December 11, 2007.
Virage Logic will be demonstrating its broadened Silicon Aware IP product portfolio with its new release of the Self-Test and Repair (STAR(TM)) Memory System, which adds capabilities to address the challenges of advanced design and process technologies while providing a dashboard of user-selectable options to manage the tradeoffs between test time, area, speed and state-of-the-art diagnostics for optimal design complexity management. The release also expands the STAR Memory System's capabilities to address process challenges with a new product option called STAR(TM) Yield Accelerator, created to boost silicon yield and accelerate time-to-volume.
TSMC will highlight the importance of a close collaborative relationship between the foundry and IP provider. Working together, mutual customers can expect to realize such key benefits as faster delivery of successful System-on-Chips (SoCs) at the advanced process nodes.
Santa Clara Convention Center, 2nd Floor Room #203/204
5001 Great America Parkway
Santa Clara, CA 95054
on December 11, 2007
11:30am – 1:30pm ~ Registration Opens at 11:30am
More info: Virage Logic Lunchinar
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