EDA News – 2007.11.09

Wi-Fi RTLS Vendors Target Vertical Markets
“While Wi-Fi RTLS vendors expand their markets horizontally, many will rely on healthy vertical markets for sustained growth,” according to ABI Research vice president and research director, Stan Schatt. “Although manufacturing will lead the vertical market for active RFID product sales, healthcare will continue to dominate vertical sales for Wi-Fi RTLS. Not all manufacturing environments lend themselves to Wi-Fi transmission, but healthcare was an enthusiastic early adopter of Wi-Fi applications, including voice over Wi-Fi. And revenue generated from healthcare purchases of Wi-Fi RTLS products will grow to over $264 million by 2012.”

Strategic Test Debuts UF2e-3027 Digitizer, Oscilloscope PCI Express Card
Strategic Test Corp has announced the UF2e-3027 digitizer / oscilloscope PCI Express card. The card has two 100 MS/s 12-bit ADCs for simultaneous sampling and up to 2 GigaSamples of on-board memory so that signal lengths of up to 10 seconds can be recorded when both channels are operating at maximum rates. Unique features of the UF2e-3027 include the options for dual-timebase sampling, synchronous digital inputs, asynchronous digital I/O and the possibility to synchronize up to 542 channels.

Varisys Launches VM31 XMC Module with PA Semi PWRficient Processor
Varisys have launched their VM31 XMC module based on PA Semi’s new PWRficient(TM) family of CPUs. The PA Semi processor delivers ground breaking performance and efficiency: performance per Watt is up to 300% better than existing embedded computing solutions. Varisys have integrated this innovative technology in a compact industry standard form factor.

Korenix Rolls Out JetI/O 6500 Ethernet-based Block I/O Module
p>Korenix is pleased to announce the launch of Ethernet-based block I/O modules — JetI/O 6500, which is a series of Ethernet-based block I/O modules for distributive monitoring and controls. The block I/O modules feature built-in RSIC-based processor with MAC, and capable of performing analog I/O, digital I/O, and temperature measurement in an Ethernet network with Modus/TCP protocol at LAN, intranet or Internet.

AR Infotek Announces Teak 3018 Network Security Appliance
AR Infotek has developed a fanless wireless network security appliance that draws just 2.4 Watts power for entry level market. The Teak 3018 is based on an x86-compatible AMD Geode processor, built in a compact steel chassis, and is fully compatible with various Linux operation systems such as Red Hat, Fedora, FreeBSD and OpenBSD. The Teak 3018 security appliances is targeting for small / medium size businesses.

GoWare Comments on Open Handset Alliance
GoWare commented on the Open Handset Alliance and Google’s announcement outlining plans for an open-source mobile operating system. This initiative validates GoWare’s own strategy that providing end users with a ground-breaking personalized mobile content experience as well as an open development environment will significantly propel the mobile web. However, in GoWare’s case, the mobile industry doesn’t have to wait for or transition to Android enabled phones or subscribe to a specific carrier to revolutionize the cell phone experience.

Flexpoint Receives Patent for Bi-directional Bend Sensor
Flexpoint Sensor Systems, Inc. (OTCBB:FLXT) announced the company received yet another patent protecting its latest development, the Bi-directional Bend Sensor. Flexpoint’s Bi-directional Sensor gives the ability to use one sensor to measure movement or flow in multiple directions. Reducing the need for two sensors, this cutting edge single layer Bend Sensor® product allows for the measurement of mechanical movement, air flow, water flow or vibration, in either direction, with just a single sensor. It can be used as a range of motion sensor or as a very durable, very reliable switch, and can be used in most harsh environments.

Temento Systems Introduces Debug-on-Demand FPGA Designs
Temento Systems ® SA announced a Debug-on-Demand model available on its website in order to decrease the cost of debug tools for FPGA designs, while having access to advanced features. FPGA designs are becoming more complex and are integrating more third-party IP’s. Either for prototyping or for production, FPGA designers cannot afford anymore “guess’n check” debug methodologies and need to think about design-for-test as early as design project starts. If 80% of design bugs can be fixed in a short period of time, the remaining 20% can take as long as 80% of the debug phases, impairing the design closure date. Design errors are more tedious to isolate and they require high-end debug technologies such as complex triggering functions or “assertion-based verification” on-chip to track down the very last functional error.