Design for Power Seminar in Japan
Sequence Design, AMD Japan, Cadence Design Systems Japan, NEC System Technologies, and HP Japan are sponsoring a low-power design seminar in Tokyo. The event will take place on Thursday, November 8, 2007, from 12:50pm to 5:30pm at Tokyo's Akihabara Convention Hall. The seminar focuses on reducing and managing power throughout the design flow. Sequence Design's President and CEO, Vic Kulkarni, will open the seminar with a corporate update and product strategy overview.
Agenda
- Technology Trends in Low Power Design for SoCs (keynote)
Dr. Kimiyoshi Usami, Professor, Shibaura Institute of Technology - How to Establish Appropriate Power Analysis Environments for SoCs
Fumihiro Minami, Group Manager of Toshiba Microelectronics - Platform Level Power Simulation and Modeling Flow Using PowerTheater
Karthikeyan, G.T., Senior Component Design Engineer, Intel Technology India - Positioning of CyberWorkBench in ESL Design and its Roadmap
Satoshi Kojima, Technical Marketing Director, NEC System Technologies - Advanced Low Power Design with CPF
Sadao Suzuki, Sr. Technical Marketing Manager, Cadence Design Systems Japan - Opteron processor technology
Hiroyuki Amano, Senior Manager, AMD Japan - Low Power Design and Optimization
Tom Miller, VP and GM at Sequence Design
More information: Design for Power (DFP) 2007 »
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