ICCAD 2007

The International Conference on Computer Aided Design (ICCAD) will be held November 5-8 at the DoubleTree Hotel in San Jose, California. In addition to tutorials, ICCAD 2007 will feature two keynote addresses, two panels, and numerous networking opportunities.

Starting on Monday, November 5, five in-depth tutorials will be held on the topics of parallel EDA algorithms, layout and post-layout variations issues and solutions, specific within-die variability issues, DFM routing and clock distribution, and deterministic modeling of timing and reliability.

  • Refactoring to Concurrency
    Will be given by Ken Wadland and Rahul Agarwal of Cadence Design Systems. This is a “hands-on” tutorial – bring your laptop and learn state-of-the-art techniques for parallel, threaded, and distributed programming.
  • Within-Die Variations in Timing: From Derating to CPPR to Statistical Methods
    Variations across a chip must be accounted for to get the benefit of DSM technologies. The advantages and disadvantages of different approaches will be covered by Chandu Visweswariah of the IBM T.J. Watson Research Center, an acknowledged thought leader in this emerging area.
  • Addressing Variations – During Layout, Post-layout and Post-Silicon
    Covers what designers can do to cope with increasing variability during the various stages of the design and manufacturing process. It will be given by Praveen Elakkumanan from IBM Corp., Raj Varada from Intel Corp., James Culp from IBM Corp., and Michael Orshansky from the University of Texas at Austin.
  • DFM Routing and Clock Distribution
    Design steps that are both critical and complex in modern IC design. State-of-the-art techniques for dealing with these complexities will be covered by David Z. Pan from the University of Texas at Austin, Eric Nequist from Cadence Design Systems, and Simon Tam from Intel Corp.
  • Modeling Deterministic Timing and Reliability Effects in Sub-65 nm Flows
    In addition to variability, IC manufacturing is limited by many predictable effects, which must be analyzed and modeled to accurately predict chip performance and reliability. These effects, and techniques for dealing with them, will be covered by Satya Pullela from Clear Shape Technologies Corp. (now Cadence Design Systems), Chandramouli Kashyap from Intel Corp., and Bruce McGaughy from Cadence Design Systems.

In addition, four embedded tutorials, which are included in the conference registration, will be provided on physical synthesis (Tuesday), nano-photonics (Wednesday), MOSFET modeling and formal verification (Thursday).

More info: ICCAD »