PCI-SIG(R), the Special Interest Group responsible for the PCI Express(R) industry-standard I/O interconnect technology, approved 8GT/s as the bit rate for the next generation of PCIe(R) architecture, PCIe 3.0. This represents the second speed increase since the initial launch of this I/O interconnect standard in 2003.
Following a six-month technical analysis of the feasibility of scaling the PCIe interconnect bandwidth, the data shows that 8GT/s can be manufactured in mainstream silicon process technology, and can be deployed with existing low-cost materials and infrastructure, while maintaining full mechanical compatibility and with negligible impact to the PCIe protocol stack. The 8GT/s bit rate represents a doubling of the delivered bandwidth by removing the requirement for the 8b/10b encoding scheme supported in prior versions of PCIe architecture, which imposed a 20 percent overhead on the raw bit rate.
The PCIe 3.0 specification will introduce a number of optimizations for enhanced signaling and data integrity, including transmitter and receiver equalization, PLL improvements, clock data recovery, and channel enhancements for currently supported topologies. The final PCIe 3.0 specifications, including form factor specification updates, may be available by late 2009, and could be seen in products starting in 2010 and beyond.
More info: PCI-SIG »