EDA News – 2007.08.16

ESC-Taiwan, EDA&T-Taiwan Feature Embedded, Design Automation Solutions
Leading technology companies, including Agilent Technologies, Atmel, Intel, Mentor Graphics, NEC, Renesas, Spansion, TSMC and UMC are scheduled to showcase the latest embedded and design automation technologies at Global Sources’ (Nasdaq: GSOL) Embedded Systems Conference-Taiwan (ESC-Taiwan) and Electronic Design Automation & Test-Taiwan Conference and Exhibition (EDA&T-Taiwan) — Asia’s longest serving technology shows.

Multiple Vendors to Ship Sub-$50 Mobile Handset by 2008
More than a dozen handset vendors will be shipping sub-$50 models by 2008. The ultra low cost handset marketplace is currently dominated by Motorola and Nokia, but Samsung, LG, and Sony Ericsson are showing increasing interest and other smaller vendors including ZTE, Kyocera, Huawei, Haier, Sagem, Ningbo Bird, Philips, and Rose Telecom are also beginning to address the market.

Cypress Rolls Out PSoC Express 3.0 Visual Embedded System Design Tool
Cypress Semiconductor Corp. (NYSE:CY), introduced Version 3.0 of PSoC Express(TM), the breakthrough visual embedded system design tool for PSoC(R) mixed-signal arrays that dramatically simplifies embedded design. The new release delivers real-time monitoring and tuning of designs, allowing designers to observe and improve the performance of designs with Cypress’s CapSense(TM) touch sensing and EZ-Color(TM) High-Brightness LED (HB-LED) control solutions.

Novas Software Announces User Conference Program
Novas Software, Inc., the leader in debug and visibility enhancement solutions for complex chip designs, announced its 2007 International User Conference program with the theme of “Enhancing Your Verification Productivity.” This sixth annual series is comprised of technical tutorials and real-world case studies developed to give chip designers practical knowledge for tackling the functional verification of large designs.

MIT Team Places First in Hardware-Software Co-Design Contest
A five-member team from the Massachusetts Institute of Technology (MIT) took home the winner’s cup in the second annual hardware/software co-design contest sponsored by the ACM-IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007). The winning design was completed using the Bluespec electronic system level (ESL) synthesis environment.

Cadence, Mentor Graphics Team on SystemVerilog Verification Methodology
Cadence Design Systems, Inc. (NASDAQ: CDNS) and Mentor Graphics Corp. (NASDAQ: MENT) announced that they will standardize on a verification methodology based on the IEEE Std. 1800(TM)-2005 SystemVerilog standard. The Open Verification Methodology (OVM) will deliver a tool-independent solution for designers and verification engineers that promotes data portability and interoperability. It delivers on the promise of SystemVerilog with established interoperability mechanisms for Verification IP (VIP), transaction-level and RTL models, and full integration with other languages commonly used in production flows. The OVM will include a robust class library and be available in source code format.

Code-Free Embedded System Design with PSoC Express Webinar
Cypress Semiconductor Corp. (NYSE:CY) announced that it will host a free online seminar that explores visual embedded design with Cypress’s breakthrough PSoC Express(TM) 3.0 design tool. The 60-minute webinar entitled “Code-Free Embedded System Design with PSoC Express,” will be presented in conjunction with CMP Media’s Electronic Engineering Times on Wednesday, August 22 at 9:00 a.m. PDT.