Broadcom to Receive $19.6 Million from Qualcomm for Patent Infringement
Broadcom Corporation (Nasdaq: BRCM), a global leader in semiconductors for wired and wireless communications, announced that a unanimous federal jury today found that certain Qualcomm Incorporated (Nasdaq: QCOM) cellular baseband chips and software infringe claims of three Broadcom patents, and awarded Broadcom $19.64 million in damages for Qualcomm’s past infringement.
Arasan Chip Systems to Showcase MIPI IP at DAC
Arasan Chip Systems, Inc. (“Arasan”), a leading supplier of reusable Intellectual Property (IP) cores, software, and associated design services, announced it is going to feature new IP for the Mobile Industry Processor Alliance (MIPI) at the 44th Design Automation Conference in San Diego (Booth 1272). Arasan will be offering two targeted presentations for interested parties.
Pro Design to Launch CHIPit v5 ASIC Prototyping Systems at DAC
Pro Design, leading supplier of high-speed ASIC and SoC verification platforms, will launch the complete new CHIPit V5 series, at booth #6678 during the 44th Design Automation Conference (DAC) June 04 – 08 in San Diego, CA. The new CHIPit V5 generation consists of three new CHIPit platforms, the CHIPit Copper Edition V5, the CHIPit Iridium V5 and the flagship the CHIPit Platinum Edition V5.
Rio Design Automation to Demonstrate RioMagic at DAC
Rio Design Automation Inc. will demonstrate RioMagic, package-aware chip design software, in Booth #5982 during the 44th Design Automation Conference (DAC) June 4-7 at the San Diego Convention Center in San Diego, Calif.
Coupling Wave Solutions to Showcase ESI Software at DAC
Coupling Wave Solutions will exhibit a new software platform able to model electrical signal integrity (ESI) during the 44th Design Automation Conference (DAC) June 4-7 at the San Diego Convention Center in San Diego, Calif.
Blaze DFM to Attend Design Automation Conference
Blaze DFM, the electrical DFM company, will have multiple presences at this year’s Design Automation and Test in Europe conference.
Fujitsu Adopts Cadence Incisive Plan-to-Closure Methodology
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, announced that Fujitsu Kyushu Network Technologies Limited has adopted the Cadence(R) Incisive(R) Plan-to-Closure Methodology for SystemVerilog verification in RTL logic design teams. The Cadence methodology was used to verify Fujitsu’s latest set of MPEG decoder modules delivering motion block decoding capabilities. It includes a proven multi-language approach to verification reuse and specifically targets logic designers who need “design with verification” capabilities that ease SystemVerilog adoption.
Cadence Enhances Design-With-Verification Flow
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, announced enhancements to the “design with verification” component of its Cadence(R) Logic Design Team Solution, resulting in significant productivity improvements for logic designers. The new capabilities dramatically reduce key verification bottlenecks, which have prevented the effective use of assertion-based verification early in the development process.
Synopsys, ARM Enhance Reference Methodology for ARM1176JZF-S Processor
Synopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, and ARM (LSE: ARM); (NASDAQ: ARMHY), announced an enhanced implementation Reference Methodology (iRM) for the ARM1176JZF-S(TM) synthesizable microprocessor that supports a wide array of aggressive power-management techniques. These silicon-proven best practices, delivered as scripts and documentation, enable the rapid implementation of the ARM1176JZF-S processor with both high application performance and low leakage power during standby operation. These practices are documented in the “Low Power Methodology Manual,” published by Springer Science+Business Media. The enhanced iRM uses the Synopsys Galaxy(TM) Design Platform, including IC Compiler and Design Compiler(R) topographical technology, to harness these advanced power-management techniques and provide a comprehensive implementation solution that reduces risk and enables predictable success. The enhanced flow provides engineers with the latest in aggressive power-management technology.
NEC Tapes Out Gigahertz Processor with Synopsys IC Compiler
Synopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, announced that NEC Electronics Corporation (TSE: 6723) has taped out its latest high-performance processor using Synopsys’ IC Compiler next-generation place-and-route solution. Targeted at the high-end computer infrastructure market, this processor uses multiple cores operating at more than a gigahertz each, nearly double the speed of the previous version. IC Compiler, with its Extended Physical Synthesis (XPS) technology, played a critical role in achieving the gigahertz performance while keeping power dissipation in the range of a few microwatts per gate.
Toshiba Designs with Synopsys IC Compiler
Synopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, announced that Toshiba Corporation has completed the release of its Orion V1.0 design kit based on the Synopsys implementation toolset including the IC Compiler place-and-route solution. With this release, IC Compiler is now available to all designers at Toshiba, delivering increased productivity across the board as well as access to unique capabilities such as truly concurrent multi-corner/multi-mode (MCMM) optimization. IC Compiler also gives Toshiba designers a highly automated multi-voltage flow with tight correlation to other Synopsys technologies such as the PrimeTime(R) SI sign-off solution and Star-RCXT(TM) extraction solution. Since its first tapeout with IC Compiler in August 2006, Toshiba has successfully completed multiple designs at 130 and 90 nanometers (nm) and test designs at 65 nm. The very latest design is a high-performance, low-power media processor for mobile applications completed in April 2007.
Sequence Upgrades Columbus Parasitic Extractors
Sequence Design announced upgrades for its Columbus parasitic extractors, aimed at high-frequency design, 65nm characterization, and analysis of simultaneous switching noise (SSN). These new features cap a line of related improvements over the past year, including Statistically Accurate Corners for 65nm interconnect, Speedview-AMS for full-custom voltage-drop and EM analysis, and Fast Rail extraction for LVS flows.
Toumaz Technology, Healthe Team on Sensium Solutions for Sports Medicine
Toumaz Technology Limited, the leading provider of ultra-low power wireless infrastructure for body monitoring solutions, announces that it has signed a Letter of Intent (LOI) with health and wellness group Healthe International Pte Ltd to jointly develop solutions for sports medicine and rehabilitation therapy applications. The agreement marks the start of a commercial collaboration to trial solutions based on Sensium(TM)-enabled ultra small size body-worn wireless monitors and Healthe’s database for elite athletes, Healthe Sport. Toumaz’s Sensium sensor interface and transceiver platform enables intelligent, ultra-low power wireless monitoring of multiple vital signs – including ECG heart rate, body temperature, respiration and activity level – in real-time, via standard PDAs, cellphones, laptops and PCs.
Nanovata Design Automation to Develop Interconnect Optimization Tools
Nanovata Design Automation Inc. has been formed to develop and market new interconnect optimization technology and tools for IC designers who are working on complex SoCs (system-on-chip) designs at 90nm, 65nm and 45nm process technologies, with an emphasis on timing, signal integrity, yield and manufacturability improvement.
MOXA Unveils ioMirror E3210 Peer-to-Peer Active Ethernet I/O Server
MOXA, a leading manufacturer of device networking products, is pleased to announce the release of the ioMirror E3210, the newest product from MOXA’s revolutionary ioMirror line of high-speed, peer-to-peer, active Ethernet I/O servers. The ioMirror peer-to-peer Ethernet I/O servers are a new generation of I/O server that use the Ethernet and IP networks to extend the distance between digital inputs and digital outputs.
TeamF1 Debuts Managed Access Point Solution for Wi-Fi Devices
TeamF1, Inc., the leader in embedded networking and security software, announced its Managed Access Point Solution (MAPS), a new comprehensive turnkey software package that combines the latest 802.11 wireless standards with field-proven networking and security components.
MontaVista Announces Vision Embedded Linux Developers Conference
MontaVista(R) Software, Inc., the leading provider of Linux(R) for intelligent devices and communications infrastructure, announced the Vision 2007 Embedded Linux Developers Conference, to be held at the Santa Clara Marriott in California, October 8-10, 2007. Hosted by MontaVista, and including platinum sponsors Freescale Semiconductor, IBM, Intel, and Texas Instruments, the Vision 2007 event is expected to bring the latest tips, techniques, and tools to hundreds of embedded Linux developers.
Bluespec to Demonstrate Synthesizable Testbench at DAC
Bluespec(TM) Inc. will demonstrate a hardware/software co-emulation environment running on EVE’s ZeBu hardware-assisted verification platform in Booth #6963 during the 44th Design Automation Conference (DAC). DAC runs June 4-7 at the San Diego Convention Center in San Diego, Calif.