Sierra Design Focuses on 65nm, 45nm Design Challenges at DAC
Sierra Design Automation, Inc., the technology leader in variability-driven IC place & route solutions, announced that the company will be hosting a luncheon panel “65/45nm Design Challenges – A Designer’s Perspective” featuring AMD, STMicroelectronics and Texas Instruments at the Design Automation Conference (DAC) held on June 4 – 8, 2007 in San Diego, California.
Virage Logic Reveals DAC Program
Virage Logic Corporation (Nasdaq: VIRL), the semiconductor industry’s trusted IP partner and pioneer in Silicon Aware IP(TM), announced it will feature an extensive program at the 44th Design Automation Conference (DAC), to be held June 4-7, 2007, at the San Diego Convention Center in San Diego, California. Virage Logic will be hosting booth #5578 in the San Diego Convention Center, Hall E.
Magma, PDF Solutions to Debut Chip Yield Simulation Solution at DAC
Magma(R) Design Automation (Nasdaq: LAVA) and PDF Solutions, Inc. (Nasdaq: PDFS) have collaborated to deliver Quartz Yield, powered by pDfx(R) SignOff, a new advanced yield simulator that enables accurate and systematic yield improvement and decreases product costs in integrated circuit manufacturing. Quartz Yield is the first commercial yield enhancement product to combine physical verification with accurately quantified yield modeling.
Magma to Feature Partners at DAC
Magma(R) Design Automation Inc. (Nasdaq: LAVA), a provider of semiconductor design software, announced a line-up of partner activities for the 44th Design Automation Conference that will showcase mutual customers’ design successes and advanced IC design ecosystems based on Magma and third-party software.
Apache Design to Hold Dynamic Power, Clock Jitter Tutorials at DAC
Apache Design Solutions, the leader in power signoff and complete silicon integrity platform solutions for system-on-chip (SoC), analog intellectual property (IP), and system designs, announced that they will be holding free technical tutorials at the design automation conference (DAC) in San Diego, California. In these tutorials, the customers will gain hands-on experience by running Apache’s RedHawk for dynamic power analysis and optimization and PsiWinder for full-chip clock jitter analysis and timing margin management.
Open SystemC Initiative Announces Events at DAC
The Open SystemC Initiative (OSCI), an independent non-profit organization dedicated to supporting and advancing SystemC(TM) as an industry-standard language for electronic system-level (ESL) design, announces its major DAC 2007 events. Open SystemC Initiative (OSCI) will host a lunch panel on June 4 and the North American SystemC User’s Group will hold their meeting on June 4.
Rockwell Automation Acquires ICS Triplex
Rockwell Automation, Inc. (NYSE: ROK) announced that it has reached an agreement by which it will acquire Industrial Control Services Group Limited (“ICS”) for £110 million (British pounds) in cash. ICS trades and does business as ICS Triplex, a leading global supplier of critical control and safety solutions to process industries. With 40 years of experience, ICS Triplex develops, delivers and maintains advanced products and solutions for high availability, fault-tolerant applications in process industry segments worldwide.
Nascentric Announces 5 Patents for IC Simulation, Analysis
Nascentric announced that the U.S. Patent Office has awarded it five patents in the area of Integrated Circuit simulation and analysis. The patents protect the intellectual property contained within its innovative Fast-SPICE simulation and analysis tool, AuSIM(TM).
ADLINK Announces 64-Channel PCI Express DAQ Cards
ADLINK Technology Inc. introduces the DAQe-2200 series of high-performance multi-functional data acquisition cards that take advantage of the high-bandwidth benefit of the x1 PCI Express(R) bus for large-scale data transfers of up to 250 MB/s. The DAQe-2200 series samples up to 64 analog channels with various input ranges (up to 10 V) and sampling speeds (up to 3 MS/s) while offering a differential mode for 32 analog channels to maximum noise elimination. This series features analog and digital triggering, 2-CH 12-bit analog outputs with waveform generation, 24-CH programmable digital I/O lines, and a 2-CH 16-bit general-purpose timer/counter—ideal for high-speed high-volume data acquisition in industrial and laboratory measurement/automation, actuator control, ultrasonic, and acoustic applications.
Sequence, Mentor Graphics Team on ESL Power Exploration Flow
Sequence Design, the EDA leader in power-aware SoC design solutions, announced a collaborative effort with Mentor Graphics that has resulted in an integrated electronic system level (ESL) power exploration flow. This project stems from Sequence’s membership in the Mentor Graphics’ OpenDoor(R) partnership program.