Breker Verification Launches Trek Functional Test Synthesis Solution
Breker Verification Systems, Inc. announced the release of its flagship product Trek, the first commercial graph based functional test synthesis tool. The tool is targeted at developing functional vectors for complex designs, and solves the problem of understanding, defining and analyzing complicated verification requirements.
Cypress to Sell PSRAM Business to Elite Semiconductor
Elite Semiconductor Memory Technology Inc., Taiwan (ESMT) and Cypress Semiconductor Corp. (NYSE:CY) announced a Technology Transfer Agreement under which ESMT will acquire Cypress’s Pseudo Static Random Access Memory (PSRAM) product line. According to the agreement, Cypress will transfer PSRAM-related intellectual property, photomasks and probe card assets to ESMT, strengthening ESMT’s memory product portfolio for handheld devices. Financial terms of the transaction were not disclosed.
ChipVision Makes ESL Technology Breakthrough
ChipVision Design Systems, the low-power specialist in electronic design automation, announced breakthrough, patented Electronic System Level (ESL) technology that lets RTL designers work interactively with system-level descriptions to generate power-optimized Register Transfer Level (RTL) code. It creates implementation trade-off options for RTL designers, and immediately and accurately implements their visualized choices. Using this technology at the system level to analyze power can result in pre-RTL energy savings of up to 75 percent, shorten time-to-results by a factor of 60, and create code that is nine times more compact. It reduces development costs by achieving results far faster than other lower-level methods. It also greatly minimizes risk because designers can explore multiple options prior to hardware design – when the impact on power reduction is the greatest – and select the most appropriate path for meeting power budgets.
Breker Verification to Develop Graph Based Functional Test Synthesis
Breker Verification System, Inc. has been founded to develop technology that will comprehensively plan for functional verification coverage and automatically generate test vectors. The company will base its products on its patented and patent-pending Graph Based Functional Test Synthesis technology, which will bridge the functional verification gap that exists between verification planning and the testbench.
Pro Design Rolls Out CHIPit V5 ASIC Prototyping Systems
Pro Design, a leading supplier of high-speed ASIC and SoC verification platforms, announced the launch of its CHIPit V5 series, the next generation of its successful CHIPit product family. The new generation of CHIPit High-Speed ASIC Prototyping Systems is based on the largest FPGA on the market, the Xilinx Virtex-5 LX330. It offers the highest flexibility, better performance, and larger capacity, all in the most effective ASIC Prototyping system ever.
T3G to Integrate Red Bend’s FOTA into Mobile Phone Reference Design
Red Bend Software, the market leader in Mobile Software Management and Firmware Over-the-Air (FOTA) updating solutions for mobile phones and modules, announced an agreement with T3G Technology, a leading TD-SCDMA handset chipset maker, to integrate Red Bend’s market-leading FOTA solution onto T3G’s mobile phone reference design platform.
SMIC Expands Anchor’s NanoScope to 65nm and Beyond
Anchor Semiconductor, the pioneer and technology leader in DFM solutions for controlling layout-to-silicon pattern transfer, and Semiconductor Manufacturing International Corporation (SMIC), the biggest foundry in China, jointly announced the expanded applications and commitment of Anchor’s market-leading NanoScope Platform solutions in SMIC’s advanced manufacturing flows at 65nm node and beyond.
Aeroflex 4550 Flying Probe Test System Offers New Options
Striving for ongoing product improvement, Aeroflex has added soft landing and partial accessibility software options to its 4550 Flying Probe test system. The Aeroflex 4550 is a powerful and flexible Printed Circuit Board (PCB) test solution designed to meet the test needs of today and, with the continued addition of new features and capabilities, it will meet tomorrow’s test needs as well.
Aeroflex 5800 ATE Systems Feature Digital Functional Test Capabilities
Aeroflex will now offer its 5800 Series ATE system with digital functional testing capabilities. Ideal for engineers performing mixed-signal testing, device programming, functional test, in-system programming, or simple protocol communications, the 5800 Series was designed with an open architecture and highly configurable structure that allows it to easily adapt to evolving Printed Circuit Board (PCB) industry standards, providing a versatile solution that can be easily upgraded to satisfy future requirements as they emerge.
Magma, Rio Design Team on Talus Vortex, Blast Fusion, RioMagic Integration
Magma(R) Design Automation Inc. (Nasdaq: LAVA), a provider of semiconductor design software, announced the availability of enhanced flip chip design support through the integration of the Talus(TM) Vortex and Blast Fusion(R) physical design systems with Rio Design Automation’s RioMagic, the electronics industry’s first package-aware chip design software. With the enhanced capabilities, Magma provides tight links between IC implementation and package design and comprehensive redistribution layer (RDL) routing and bump placement capabilities, allowing designers to make packaging and performance tradeoffs and decisions earlier in the design process to ensure better quality of results (QoR), faster turnaround time and optimal packaging.
Cadence Introduces Low-Power Methodology Kit
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, announced the industry’s first kit that enables engineers of different experience levels to adopt advanced low-power techniques with minimized risk and deployment effort. A complement to the Cadence(R) Low-Power Solution, the Cadence Low-Power Methodology Kit provides a working end-to-end methodology covering logic design, functional verification and physical implementation. The Kit includes example IP, scripts and libraries; all proven on an included wireless segment representative design. Delivered together with Cadence applicability consulting services, the Kit enables design teams without extensive low-power implementations to quickly optimize their low-power design environment, and accelerate their time to lower power, more competitive system-on-chip products.
Chinese Vendors Adopt Verification Methodology Manual for SystemVerilog
Synopsys, Inc. (Nasdaq:SNPS), a world leader in semiconductor design software, announced that the VMM verification methodology, described in the ARM-Synopsys Verification Methodology Manual (VMM) for SystemVerilog, has been adopted by major electronics companies in China for developing advanced verification environments. In addition, Synopsys announced that the Chinese-language edition of the manual has been published by Beihang Press in China. More than 3,500 copies of the English-language edition have been sold to date.
Mentor Graphics Expands Questa Verification Solution
Mentor Graphics Corporation (Nasdaq: MENT) announced it has expanded the comprehensive Questa(TM) verification solution, which combines tools, methodology and industry partners to deliver a new level of verification productivity and efficiency to today’s designers. The announcement includes the new Questa 6.3 functional verification platform addressing low-power verification, and powerful verification management capabilities that enable closed-loop management reporting, analysis and documentation. It also includes improved debugging and version 3.0 of the industry’s first open-source standards-based Advanced Verification Methodology (AVM).