Tips for FPGA Timing Closure

Lattice is offering a webcast for FPGA designers. The one-hour event will take place Wednesday, March 28, 2007 at 11:00 am Pacific time (2:00 pm Eastern). Here’s the webinar blurb:

FPGA designers often find themselves squeezing every last bit of performance out of the least expensive, slowest speed grade, device available. In this presentation, Lattice Semiconductor provides practical advice on how a combination of RTL style, constraints, and optimization options can be applied to produce the most efficient FPGA implementation.

One participant who attends the live broadcast and fills out the feedback form will receive either an ispLEVER Development Tool for Lattice programmable logic design or a spaceship.

Troy Scott is a marketing specialist at Lattice Semiconductor Corporation. He has more than 15 years experience in the EDA and semiconductor industry. Troy’s background includes HDL synthesis and simulation, hardware emulation, and IP evaluation and marketing. Troy holds a BSCE from Oregon Institute of Technology and a Graduate Certificate in Computer Architecture and Design from Portland State University.

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