The new ICCAD Executive Committee is issuing a Call For Papers (CFP) for ICCAD 2007. Submissions are encouraged in high-growth, high-challenge areas of electronic design. Selected submissions will be a fundamental piece of ICCAD 2007′s Program. In this program, Nanotechnology will remain a key growth area for the ICCAD, as it has been taking an industry-leading role. In addition, the Designers’ Perspective initiative remains a major thrust that will repeat and grow in 2007. The Program will also contain tutorials and number of panel discussions.
The deadline for submissions is April 11, 2007 at 5:00pm MDT.
ICCAD is covering the full range of traditional CAD topics. In addition, ICCAD is focusing on CAD for supporting the transition beyond CMOS, which will include a variety of mixed domain designs. Original technical submissions focusing on, but not limited to, the following topics are invited:
1) PHYSICAL DESIGN
1.1 High-Level physical design and synthesis. Estimation and hierarchy management. Partitioning, floor-planning and global placement. Detailed and incremental placement.
1.2 Routing and detailed physical design. Detailed routing, post-placement layout and optimization. Clock network design.
1.3 Interaction between physical design and logic synthesis. Optimization for area, timing, power, and yield.
2) SYNTHESIS, VERIFICATION AND SYSTEM DESIGN
2.1 Synthesis, technology mapping. Refinement techniques. Direct compilation and post-optimization. Micro-architectural transformations. Memory system synthesis.
2.2 System design. HW and SW co-optimization and co-exploration. Multi-processor systems (heterogeneous, homogeneous, reconfigurable). On-chip communication optimization. HW/SW platforms.
2.3 Embedded and programmable systems. Real-time software and RTOS. Reuse techniques. Rapid prototyping, CAD for FPGA.
2.4 Formal verification techniques. HW/SW co-simulation. Switch, logic and behavioral simulation, and design validation. Protocol and interface design for correctness. Software verification. Emulation.
3) DESIGN FOR MANUFACTURING AND TEST
3.1 CAD for the design/manufacturing interface, CAD support for OPC and RET, variability analysis, yield estimation.
3.2 Novel ideas in layout and physical implementation: manufacturable layout. Design for resilience and robustness.
3.3 Testing. Fault modeling, delay test, analog and mixed signal test. Fault simulation. ATPG. BIST and DFT. Memory test and repair. Technology impact on test.
4) MODELING AND SIMULATION
4.1 Design and CAD for analog, RF, and mixed signal. EMC/EMI simulation techniques.
4.2 Gate, switch, and circuit level timing. Circuit simulation.
4.3 Power estimation, power analysis, power/ground and package analysis and optimization.
4.4 Mixed technology design, thermal analysis, and reliability analysis, MEMS.
4.5 Interconnect parameter extraction. Circuit model generation. Signal integrity analysis.
5) DESIGN TECHNOLOGIES FOR FUTURE AND POST CMOS
5.1 Trends and perspectives in system-level design, with emphasis on power, software, performance and configurability: SoC, SiP, 3-D integration, programmable and reconfigurable platforms.
5.2 Novel circuit and system implementation styles: new circuit families, fault- and variations-tolerant circuits, resilient and regular circuits, and structured ASICs.
5.3 Alternative technologies. Modeling, simulation, analysis and design methods for novel device structures: nanotechnology, quantum, molecular and bioelectronics.