DVCon SystemC Events

The Open SystemC Initiative (OSCI) will be conducting SystemC events in conjunction with the Design and Verification Conference (DVCon 2007) in San Jose, CA.

North American SystemC Users Group (NASCUG) Meeting
Wednesday, Feb 21st, 8:30 am to 1:00 pm
NASCUG provides a format for users to learn, interact and discuss techniques of design, modeling and verification using SystemC. Topics include: architectural modeling, transaction-level modeling, hardware/software co-design, and verification techniques using SystemC. Suppliers will also present the latest SystemC offerings from our sponsors. Featured companies include ARM, Cadence, CoWare, Forte, Mentor Graphics, Synopsys, ESLX, and Doulos. Registration is free for industry professionals.

DVCon Tutorial
SystemC Transaction Level Modeling Standards and Methodology Guidelines

Wednesday, Feb 21st, 1:30 pm to 5:00 pm
The successful adoption of TLM depends on the interoperability of models from multiple sources at multiple abstraction levels. Right now, this means the need to support models of common on-chip busses at the Programmers View (PV) level, to annotate timing onto those models (PVT) and to support Cycle Accurate (CA) modeling. Addressing the challenges of interoperability at these modeling levels, OSCI released TLM 2.0 for public review in Dec. 2006. This tutorial will present an in-depth discussion and examples of the many technical issues raised and addressed by TLM 2.0. Registration for this tutorial requires a $50 fee or conference registration with DVCon.

Location
Doubletree Hotel, Fir Ballroom
2050 Gateway Place, San Jose, CA 95110

free Portable Design