EDA News – 2006.10.23

  • Sequence Celebrates Diwali Festival Of Lights
    Chip-design software pioneer Sequence Design typically burns the midnight oil trying to reduce power in today’s multi-million-transistor circuits, but during the Hindu festival of Diwali, widely known as India’s “Festival of Lights,” CEO Vic Kulkarni turns up the wattage.
  • Northrop, Nallatech to Create FPGA-Based Satellite Test Platform
    Nallatech, the leader in high-performance FPGA computing solutions, today announced its collaboration for developing a test platform for space borne processing with Northrop Grumman Corporation’s (NYSE: NOC) Space Technology sector, a developer of systems at the leading edge of space, defense and electronics technology. Northrop Grumman Space Technology creates sophisticated products that contribute significantly to the nation’s security and leadership in science and technology. Work on the FPGA system development for Northrop Grumman aligns with Nallatech’s focus on the U.S. defense and aerospace markets.
  • LynuxWorks Creates LynxOS RTOS BSP for Radstone PowerPC 7D SBC
    Expanding on its already robust support capabilities for developers of military and defence embedded applications, LynuxWorks, Inc., today introduced a LynxOS real-time operating system (RTOS) board support package (BSP) for Radstone Technology’s PowerPC 7D (PPC7D) single board computer, which offers rugged commercial off-the-shelf (COTS) embedded systems for defence applications.
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  • Ramtron Receives AEC-Q100 Qualification for 16Kbit 3V Serial FRAM
    Ramtron International Corporation (Nasdaq: RMTR), a leading developer and supplier of non-volatile ferroelectric random access memory (FRAM) and integrated semiconductor products, today announced that its FM24CL16 – a 16Kbit, 3V serial FRAM memory device – has been qualified to AEC-Q100 (Automotive Electronic Council’s Stress Test Qualification for Integrated Circuits) standards. Ramtron is aggressively pursuing plans to grow a broad line of AEC-Q100-qualified FRAM products to meet the design and sourcing challenges of the automotive market. This qualification program has been developed to support a number of customer design-ins from in-cab applications to the vehicle’s most stringent environments.
  • CoWare to Discuss EDA Challenges for Complex SoC and ASIC Designs
    CoWare(R), Inc., the leading supplier of platform-driven electronic system-level (ESL) design software and services, announced that it will participate in a panel discussion entitled “EDA Challenges for Complex SoC and ASIC Designs” at the 4th International System-on-Chip (SoC) Conference & Exhibit, November 2 in Newport Beach Calif.
  • RTI Real-Time Connect Integrates Enterprise with Real-Time Systems
    Real-Time Innovations (RTI), The Real-Time Middleware Company, today introduced RTI Real-Time Connect, a solution for integrating enterprise applications with real-time applications, data and devices. RTI Real-Time Connect overcomes the challenges traditionally associated with integrating enterprise and real-time systems in a number of ways: preventing high-throughput real-time applications from overwhelming slower enterprise infrastructures, delivering immediate real-time notification of enterprise events to real-time applications and bridging between disparate middleware and data management standards.
  • Cadence Logic Design Team Solution Features Concurrent RTL Design
    Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, today introduced the Cadence(R) Logic Design Team Solution, which allows concurrent RTL design, enabling schedule predictability. This unique solution equips logic design teams with the elements they need ­– from verification and power to test and physical – plus plan-to-closure management and logical signoff­ in an integrated and holistic approach. It represents another deliverable in Cadence’s overall segmentation strategy, offering tailored solutions for specific types of engineering teams.
  • Celoxica Introduces FPGA Co-Processing Package for Hypertransport
    Celoxica (LSE:CXA), a member of the HyperTransport Technology Consortium, today announced availability of the first complete off-the-shelf hardware and software compiler design bundle for High-Performance Computing (HPC) using industry standard HyperTransport (HTX) slots. The HTX bundle combines an intellectual property (IP) core for HTX compliant connectivity, an FPGA-based HTX acceleration card and a comprehensive software-programming environment.
  • Microchip Announces MCP1702 250 mA Low Dropout Regulator (LDO)
    Microchip Technology Inc., a leading provider of microcontroller and analog semiconductors, today announced the MCP1702 Low Dropout Regulator (LDO) — a 250 mA LDO with low quiescent current, high input voltage, over-voltage protection and thermal shutdown on a single chip. The new LDO is ideal for applications requiring long battery run-times and high tolerance for input-voltage variations, such as smoke detectors, fire alarms, and commercial and residential thermostats.
  • Micrium’s uC/OS-II RTOS Ports to LatticeMico32 Soft Microprocessor
    Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the availability of Real-Time Operating System (RTOS) support for its LatticeMico32(TM) open source 32-bit soft microprocessor. A port of Micrium’s uC/OS-II RTOS is included with the latest version of the LatticeMico32 Development Tools, which is being released concurrently with Lattice’s award-winning ispLEVER(R) software design tool suite, Version 6.1. The combination of the LatticeMico32 microprocessor and the uC/OS-II RTOS allows users to rapidly develop embedded systems, particularly performance sensitive real-time systems.
  • Lattice Rolls Out ispLEVER 6.1 Programmable Logic Design Tool Suite
    Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of its ispLEVER(R) 6.1 programmable logic design tool suite. Version 6.1 adds new design resources and productivity enhancement tools for designers, including the innovative HDL Explorer(TM) tool that helps manage and analyze large FPGA designs. The ispLEVER 6.1 release supports Lattice’s latest FPGAs, including the new LatticeECP2M(TM) FPGA family, the new LatticeMico32(TM) System for 32-bit microprocessor design and enhanced third-party synthesis and simulation tools. Combined with numerous other improvements, the ispLEVER 6.1 tool suite is an extremely powerful programmable logic design solution.
  • Mercury Ports Serial RapidIO IP to LatticeSC Extreme Performance FPGA
    Lattice Semiconductor (NASDAQ: LSCC) today announced that Mercury Computer, a computing solutions provider to government, defense, energy, medical and telecommunications providers, has ported its high-performance Serial RapidIO(R) Intellectual Property (IP) product line, consisting of x1 and x4 endpoint IP cores, to the LatticeSC(TM) family of 90nm (nanometer) Extreme Performance(TM) FPGAs. In addition, Mercury has joined Lattice’s ispLeverCORE(TM) Connections IP partner program. Working together, Mercury and Lattice will develop and deliver complete system solutions for mutual customers requiring high-performance Serial RapidIO connectivity supported by Lattice’s FPGA product families.