Fall Microprocessor Forum

Posted by Ken Cheung in Microcontrollers on Tuesday, October 3, 2006
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The Fall Microprocessor Forum will take place next Monday, October 9th in San Jose, California. The event will feature:

  • Low Power Seminar with tutorial on low power for mobile processors and cooling techniques for very-high-performance engines
  • Presentation by Cadence on low power design tools
  • Presentation by Texas Instruments on the application of low power technologies to system-on-chip design
  • CoWare will present its approach to create SoCs employing accelerators for better power reduction
  • Nextreme Thermal Solutions will explain how to cool hot spots on chips running at high frequencies without dropping frequency and voltage

Fall Microprocessor Forum's conference will be highlighted by four keynotes from the following companies in low-power desktop and server processors, design tools, handheld engines, and operating systems:

  • ARM
  • Intel
  • Cadence
  • Microsoft

Harlan McGhan, formerly with Sun, will chair a strong session on server microprocessors showcasing papers from Fujitsu, IBM, and Sun Microsystems & Emulex. Tom Halfhill, Senior Analyst with In-Stat will moderate a session presenting new processor cores, and he and Max Baron, Principal Analyst and conference content chairperson, will share a two-part mega-session focusing on massively parallel processors positioned to take advantage of the rising costs of SoCs employing sub-90nm process technologies.

The conference will close with a new type of session for Fall Microprocessor Forum: Max Baron will chair a session on Multimedia at the Hardware- Software Interface. Aimed at chip and system designers, the session includes informative and educational papers on the latest chip introductions and the selection of the software to make them shine.

Fall Microprocessor Forum
October 10-11
Doubletree Hotel
San Jose, California

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