EDA News – 2006.10.02

  • Force10 Receives Patents for 100 Gigabit Ethernet-Ready Backplane
    Force10 Networks(R), the pioneer in building and securing high performance networks, today announced that it has been awarded two patents for its advanced 100 Gigabit Ethernet-ready backplane. The unique, patent-protected backplane of the Force10 TeraScale E-Series(R) family of switch/routers has been tested up to five Terabits per second, delivering 330 Gigabits per second (Gbps) to each slot. Force10 now holds 15 patents with 45 patents pending.
  • Semiconductor Sales Grows by 10.5% to $20.5 Billion in August
    Worldwide sales of semiconductors reached an all-time monthly record of $20.5 billion in August, an increase of 10.5 percent from the $18.6 billion reported in August 2005, the Semiconductor Industry Association (SIA) reported today. Sales increased by 2.1 percent from July 2006, when total semiconductor sales were $20.1 billion. The previous record for one-month worldwide chip sales was $20.4 billion in November 2005.
  • TI Drives Over 300 Watts on Single Channel with PurePath Digital
    Texas Instruments Incorporated (TI) (NYSE: TXN) today introduced two new PurePath Digital(TM) power stages. The TAS5261 provides OEMs with the industry’s highest power single-chip digital amplifier power stage, capable of driving more than 300 watts (W) into a 4-ohm speaker, while the two-channel TAS5162 digital amplifier power stage can drive 200 W per channel at 6 ohms and 125 W at 8 ohms. The devices enable higher efficiency and sound quality in a variety of audio applications, including many previously restricted from using digital amplifiers due to power requirements, such as high-end DVD receivers and mid- to high-end audio/video receivers (AVRs).
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  • Displaytech Selects Synopsys Design Compiler Tool for FLCOS Microdisplays
    Synopsys, Inc. (Nasdaq: SNPS), a world leader in semiconductor design software, today announced that Displaytech Inc., a world leader in ferroelectric liquid-crystal-on-silicon (FLCOS) microdisplays, has moved to the Synopsys Design Compiler(R) synthesis tool in designing its next-generation FLCOS backplane for high-resolution, high-speed microprojection and holographic data storage (HDS) systems. These new microdisplays deliver high-speed light switching to produce brilliant, real-life digital images. The advanced timing and power synthesis capabilities in the Design Compiler tool proved crucial in meeting Displaytech’s design goals within schedule.
  • Xilinx Offers ESL for FPGA Workshop
    Xilinx, Inc. (Nasdaq: XLNX) today announced the first ever ESL for FPGA workshop to be held in San Jose, Calif., on November 6, 2006. The event will provide an opportunity for the design community to experience first hand the value and immediate benefits of the emerging electronic system-level (ESL) methodologies as they apply to field programmable gate array (FPGA) design.
  • Ardence, Intel Accelerate Development of Embedded Virtual Technology
    Ardence, the global leader in developing software platforms for the on-demand world, today announced a collaborative effort with Intel to accelerate the development of virtual technology in embedded environments. Ardence said it will begin testing its market-leading embedded software products in conjunction with Intel(R)’s Virtualization Technology (VT) in various OEM-usage scenarios to develop performance data that will be used to enhance next-generation embedded systems. In addition, this data will be utilized by the developers of next-generation embedded systems to further understand and promote best practices in order to optimally leverage Ardence and Intel technologies.
  • Fastrax Expands in Korea and China
    Fastrax Ltd., a leading provider of open and portable iSuite OEM GPS Software Development Kit environments and programmable iTrax OEM GPS receivers, today announced two new distributor agreements that strengthen the company’s position in the fast-growing OEM electronics market in Asia.
  • Cadence, Brion, Clear Shape Create Lithography-Aware Design Flow
    Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, today announced that it has created a lithography-aware design flow and has defined an interface that will link resolution enhancement technologies (RET) with physical design and verification. Cadence has collaborated with Brion Technologies and Clear Shape Technologies in developing this flow which addresses critical lithography-induced yield problems and mask-design challenges.
  • Loterie Nationale Rolls Out Comtech Jackpot Communicator
    Loterie Nationale, the operator of Luxembourg’s National Lottery and Comtech M2M, a leading Machine-to-Machine (M2M) solution provider, today announced the deployment of the Comtech jackpot communicators (“JPCs”) across Loterie Nationale’s full network of lottery retailers.