EDA News – 2006.09.05

  • Texas Memory, HMK Blaze Across Europe with World’s Fastest Storage
    Texas Memory Systems, Inc. (TMS), makers of the World’s Fastest Storage(R), today announced a resale agreement with Germany-based HMK Computer Technologies GmbH. Under the agreement HMK will help large enterprises, research facilities, and universities across Europe to accelerate databases and scientific applications using Texas Memory Systems’ RamSan solid state disks.
  • Tricomtek to Distribute ClearSpeech Voice Technologies in Korea
    Cambridge voice technology specialists, NCT, have appointed Tricomtek in Seoul, Korea as a reseller of their ‘ClearSpeech’ voice technologies for the Korean region. Tricomtek will resell NCT’s noise cancellation, echo cancellation and voice enhancement technologies to developers of voice communication products such as mobile phones, radio systems and Bluetooth wireless technology.
  • SMIC, Synopsys Create Reference Design Flow 3.0 for 90nm Designs
    Synopsys, a world leader in semiconductor design software, and Semiconductor Manufacturing International Corporation (SMIC), the largest foundry in China, today announced that the two companies have jointly developed and deployed reference design flow 3.0. SMIC and Synopsys Professional Services worked together closely on the complete RTL-to-GDSII flow, which is based on the Synopsys Galaxy(TM) Design and Discovery(TM) Verification Platforms and SMIC’s advanced 90-nanometer (nm) process. The proven flow incorporates a broad range of automated low-power and design-for-manufacturing (DFM) capabilities to shorten time-to-market, reduce risk and ensure predictable success for complex system-on-chip (SoC) designs.
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  • Calypto, Golden Gate and Sequence Join Power Forward Initiative
    In response to strong industry support to quickly establish a single, open standard for power intent, the Power Forward Initiative (PFI), today announced that it continues to garner broad industry support for the standardization of the Common Power Format (CPF). EDA companies Calypto Design Systems, Inc., Golden Gate Technology Inc. and Sequence Design, Inc. are the latest to join the Initiative.
  • Fujitsu Signs Off with Cadence Encounter Timing System (ETS)
    Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Fujitsu Limited has adopted Cadence(R) Encounter(R) Timing System (ETS) for timing analysis in their implementation flow. ETS delivers superior signoff timing accuracy, usability and functionality for designs at 90 nanometers and below.
  • Cadence Encounter Timing System Offers Superior Signoff Analysis
    Cadence Design Systems today further extended the capabilities of the Cadence(R) Encounter(R) digital IC design platform with the announcement of its Encounter Timing System. This new system provides customers a single source and consistent view of timing, signal integrity and power — from design and physical implementation, through final signoff analysis. In addition to addressing the needs for implementation and signoff analysis, front-end design teams will also benefit from its global timing debug features for accurate root-cause analysis and fast timing closure, which is driven by a powerful graphical user interface.