What’s New on Embedded Star – 2006.08.18

Embedded Star added the following FPGA design tools to their directory:

  • Synplicity’s Tools for Structured ASIC and Prototyping
    Synplicity’s tools for Structured ASIC and prototyping consist of Amplify AccelArray Pro, Amplify ISSP Pro, and Certify . The Amplify AccelArray Pro solution provides an integrated flow with Fujitsu’s AccelBuilder software, and directly reads AccelArray physical and logical libraries. The Amplify ISSP Pro solution provides an integrated flow with NEC Electronics’ OpenCAD software, and reads ISSP physical and logical libraries from the NEC Electronics ISSP design kit. Certify ASIC prototyping solution is the leading product for ASIC prototyping using multiple FPGAs.
  • Lattice Design Software
    Lattice’s products are supported by their ispLEVER 6.0 software development tool suite and PAC-Designer(TM) software. Supporting the PC, UNIX and LINUX platforms, ispLEVER software allows customers to enter, verify and synthesize a design, perform logic simulation and timing analysis, assign input/output pins, designate critical paths, debug, execute automatic timing-driven place and route tasks, and download a logic and input/output configuration to one of Lattice’s devices. Designed to seamlessly integrate with third-party electronic design automation environments, ispLEVER software provides a front-to-back design flow that leverages a customer’s prior investment in tools offered by Cadence, Mentor Graphics, Synopsys and Synplicity.
  • Actel FPGA Software Tools
    Actel’s tools for FPGA development and physical implementation consist of Libero Integrated Design Environment (IDE) and Designer. Actel’s Libero IDE offers the latest and best-in-class tools from leading EDA vendors such as Magma Design Automation, Mentor Graphics, SynaptiCAD, and Synplicity. Designer is Actel’s powerful physical implementation software tool suite.
  • Xilinx’s FPGA Software Design Tools
    Xilinx offers a variety of FPGA design software for logic design, DSP design, and embedded processing design. Their design tools consist of ISE Foundation, ISE WebPACK, ISE Classics, Platform Studio and the EDK, System Generator for DSP, AccelDSP(TM) Synthesis Tool, ChipScope Pro, ChipScope Pro Serial IO Toolkit, PlanAhead, and ModelSim Xilinx Edition-III.
  • Altera’s Design Software for FPGA, CPLD, and Structured ASIC
    Altera offers design software for FPGA, CPLD, and structured ASIC devices. Their design tools consist of Quartus(R) II, Quartus II Web Edition, SOPC Builder, ModelSim(R)-Altera, and Nios(R) II IDE. Quartus II software supports all of Altera’s latest device families. Quartus II Web Edition software is a subset of Quartus II software. SOPC Builder is an automated system development tool. The ModelSim-Altera software is an Altera-specific version of the Model Technology(TM) ModelSim simulation software. The Nios II Integrated Development Environment (IDE) is the primary software development tool for the Nios II family of embedded processors.