EE Times FPGA Users Survey

According to the EE Times 2006 EDA Users Survey, FPGA complexity and speed are rapidly increasing, and as a result, FPGA designers are confronting many of the same issues — and adopting some of the same tools — as their counterparts in ASIC and IC design. Here are some excerpts:

Engineers are expecting average gate counts of around 4 million within two years. While meeting timing budgets is the prime concern today, our North American FPGA respondents, just like the respondents to the ASIC portion of the survey, said that leakage current is getting notably worse as silicon geometries shrink.

There are other ways in which the FPGA survey results mirrored those in the ASIC survey. In both cases, EDA budgets are rising faster in Asia. In both surveys, designers are most satisfied with the accuracy of their EDA tools, and least satisfied with pricing and interoperability. And in both surveys, North American designers were generally more satisfied with tools and vendors than respondents to EE Times’ 2005 survey, which focused on North America only.

The 2006 survey also shows that tools and technologies from the ASIC world are seeing broader acceptance. Huge majorities are using FPGA synthesis, HDL simulation and FPGA floor planning, and there’s growing interest in hardware/software co-design, power analysis, SystemVerilog and C-language synthesis.

Source: EE Times