Some chip and systems companies are seeing benefits from experiments and limited adoption of System Verilog, mainly in back-end design areas such as verification. However, poor vendor support for the high-level design language is holding back broader deployments. Each vendor supports a different subset of System Verilog features, which makes it very hard for users to track who supports what features for what functions.
Users need consistent support from all vendors in the industry, at least for a subset of synthesis and simulation features. Currently some features are supported in simulation but not synthesis and vice versa.
Source: EE Times