EE Times released the results of their 2006 EDA Users Survey. According to the survey, design tool users are most satisfied with EDA technology and accuracy, and least satisfied with pricing, licensing and interoperability. Chip designers today are most concerned about functional verification and timing closure. But as feature sizes shrink, they expect that managing leakage current will become their biggest concern—even bigger than design-for-manufacturability (DFM).
Source: EE Times 2006 EDA Users Survey