Cadence decided to address obstacles to lower power IC design by forming the Power Forward Initiative. The goal of the Power Forward Initiative is to enable the design and production of more power-efficient electronic devices.
The Initiative will link design, verification and implementation to reduce risk and increase predictability in chip power reduction. Members will work to adopt a new automated design infrastructure aimed at reducing chip power consumption. To achieve its goal, the Power Forward Initiative charter calls for the refinement and promotion of a new open specification that captures essential design intent for power and links the design, implementation and verification domains. The group aims to begin the industry open standardization process starting in 2007.
Recognizing the need for a broad-based method of specifying power-management design intent across the entire design chain and for ensuring smooth collaboration and high-yield manufacturability, the Initiative members will have access to the first version of the Common Power Format (CPF). This new specification language addresses the limitation in the design automation tool flow by capturing the designer’s intent for power management. The Common Power Format enables all design- and technology-related power constraints to be captured in a single file and applies that file across the design flow, providing a consistent reference point for design development and production.
It looks like Cadence have some big names in their camp. Members of the Initiative include Advanced Micro Devices (AMD), Applied Materials, ARM, ATI Technologies, Freescale Semiconductor, Fujitsu, NEC Electronics, and Taiwan Semiconductor Manufacturing Company (TSMC). So, what about the other two big EDA companies, Synopsys and Mentor Graphics?