Virage Logic and Cadence is offering a web seminar titled, “Advanced Design Methodology for Low-Power Applications: An Integrated RTL-to-GDSII Approach.” The live seminar will take place Wednesday, May 24, 2006, at 1:00 p.m. EDT. You can register online for the seminar.
Here’s the abstract for the webinar:
Power reduction is a critical requirement that is affecting most designs at 90nm and below. Traditional low-power design techniques such as clock gating and mixed-Vt optimization are no longer adequate enough to meet power budget constraints. Designers need to adopt advanced low-power techniques in order to achieve significant power reduction. This informative webinar will demonstrate how low-power designs implemented with Virage Logic’s Ultra-Low-Power Semiconductor IP in conjunction with the Cadence(R) Encounter(R) digital IC design platform can meet today’s rigid power budgets. This complete low-power design flow implementation addresses time-to-market and silicon success challenges, enabling designers to use advanced techniques with confidence for low-power designs all the way from RTL-to-GDSII.