Real Intent launched version five of their Meridian CDC tool. The new hierarchical CDC flow supports partitioned analysis of designs without sacrificing top-level full-chip precision for giga-scale sign-off. Meridian CDC’s hierarchical flow avoids the compromises found with abstract-modeling and the use of waivers in other products. Meridian CDC v5.0 will be available July 1, 2013. Pricing depends on product configuration.
Synopsys has extended their DesignWare Duet Embedded Memory and Logic Library IP to enable the optimized implementation of a broad range of processor cores. In one package, designers now have access to the specialty cells and memories they need to optimize their CPU, GPU and DSP cores across the full speed, power and area spectrum. The DesignWare HPC Design Kit will be available for leading 28-nm processes starting in July of this year.
Synopsys has developed a new test technology to further reduce the cost of testing silicon devices by delivering up to 3x higher test compression and minimizing the time required to test each silicon die. The new test technology is embedded in Synopsys’ Design Compiler RTL synthesis and TetraMAX ATPG solutions. Synopsys’ synthesis-based test innovation will help engineers meet more stringent test cost and quality goals within tighter design schedules.
Modelithics released version 10.1 of their COMPLETE Library of passive and active device models for AWR’s Microwave Office high-frequency design software. Modelithics’ scalable measurement-based models are designed to work seamlessly within AWR’s circuit design software. Modelithics COMPLETE Library v10.1 includes more than 8600 individual components. The Modelithics COMPLETE library can be licensed directly through AWR either as an add-on module to or as part of an AWR Microwave Office bundled configuration.
Mentor Graphics has added cache coherent interconnect subsystem verification to the Questa and Veloce platforms. ARM AMBA 5 CHI and AMBA 4 ACE specifications enable high performance, coherent SoC design functionality to be at the heart of the Questa and Veloce platforms. The Questa and Veloce platform AMBA 4 ACE verification solutions are available now. The AMBA 5 CHI verification solutions are available to approved ARM AMBA 5 CHI licensees.
Synopsys introduced the DesignWare ARC EM Starter Kit for the ARC EM family of embedded processor cores. The DesignWare ARC EM Starter Kit, ARC EM4 and ARC EM6 processor cores and associated development tools are available now. The DesignWare ARC EM4 and ARC EM6 processor cores are optimized for use in embedded and deeply embedded applications such as sensors, storage devices, appliances, consumer electronics, and battery-operated devices where high performance, small size and minimal power consumption are essential.
The 50th Design Automation Conference (DAC) is taking place this week. The conference features SKY Talks, DAC Insights, Training Day and Visionary Talks from industry luminaries. The 2013 event will take place at the Austin Convention Center in Austin, Texas from June 2-6, 2013. DAC is dedicated to the electronic design, design automation, IP, embedded systems and software industries.
CommandFusion introduced the iViewer Lite iOS app. The mobile application helps DIY users and installers of smaller automation systems to create their own custom graphical user interfaces (GUIs). iViewer Lite is available on the Apple App Store for $49.99. The app is compatible with all iOS devices running an iOS version of 4.3 or higher.
Synopsys introduced the Virtualizer Development Kit for Renesas RH850 microcontrollers. The VDK accelerates software development, system integration and test for RH850-based automotive applications such as body, powertrain/hybrid and chassis/safety control. The new development kit seamlessly integrates into existing software development flows. The VDK makes it easy for engineering teams throughout the automotive supply chain to deploy and achieve higher levels of product reliability, reduce overall development cost and shorten design cycles. The VDK for Renesas RH850 MCU is available now.
Cadence Design Systems has issued a call for papers to be presented at MemCon 2013. Cadence is seeking presentations and papers on topics that illustrate users’ knowledge and expertise in memory design and architecture. The deadline for paper abstract submission is May 30, 2013. The MemCon conference showcases the thought leaders driving advances in memory technology. The event will take place August 6, 2013 at the Santa Clara Convention Center.
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