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Apache Design Sponsors Two DesignCon Chip Package System Workshops

Posted by Ken Cheung in Events, Training on Friday, January 27, 2012

Apache Design, Inc. is sponsoring two Chip-Package-System (CPS) workshops at DesignCon 2012. The two in-depth technical workshops will provide designers with an open forum for exchanging the latest ideas and information on the most current technologies. In the interactive workshops, leading semiconductor companies and system houses will share perspectives and best practices on chip and package modeling, and system-level verification for signal integrity, power integrity, electromagnetic interference and thermal. The workshops are free. However, seating is limited and registration is required.

Apache Design Sponsors Two DesignCon Chip Package System Workshops »

HSPICE 2011.09 Speed-up Signal Integrity Simulation by Factor of Three

Posted by Ken Cheung in Models, Simulations on Thursday, January 26, 2012

HSPICE 2011.09 has been integrated with Sigrity’s signal integrity analysis solution to accelerate signal integrity simulation of high-speed systems. The combined Synopsys and Sigrity tool features up to 3X faster simulation of signal and power integrity analysis of multi-gigahertz designs. In addition, HSPICE 2011.09 circuit simulator offers enhanced multi-core simulation performance, improved accuracy in statistical eye-diagram analysis, and new multi-core enabled S-parameter and W-element analysis.

HSPICE 2011.09 Speed-up Signal Integrity Simulation by Factor of Three »

Non-Intrusive Board Bring-Up: Software Tools Ensure Fast Prototype Bring-Up White Paper

Posted by Ken Cheung in Research on Wednesday, January 25, 2012

ASSET InterTech recently published a white paper titled: Non-Intrusive Board Bring-Up: Software Tools Ensure Fast Prototype Bring-Up. The technical paper explains how non-intrusive software tools can bring up prototype circuit boards faster than legacy hardware-oriented tools like oscilloscopes and logic analyzers. The white paper reviews best practices for board bring-up and describes the benefits of integrating non-intrusive tools based on embedded instruments into an organization’s board bring-up framework.

Non-Intrusive Board Bring-Up: Software Tools Ensure Fast Prototype Bring-Up White Paper »

Webinar: Understanding the Basics of Parallel Wafer Level Reliability

Posted by Ken Cheung in Events, Training on Tuesday, January 24, 2012

Keithley Instruments, Inc. will host a one-hour webinar about parallel wafer level reliability testing. The free webcast will take place Thursday on January 26, 2012. It will be broadcast twice: 15:00 CET (9:00 AM EST) and 2:00 PM EST. The title of the online seminar is Understanding the Basics of Parallel Wafer Level Reliability. The webinar is ideal for engineers who are new to semiconductor reliability testing, test engineers who need to accelerate WLR testing, and QRA lab managers.

Webinar: Understanding the Basics of Parallel Wafer Level Reliability »

ADI Webinar: The Latest on Driving ADCs Differentially

Posted by Ken Cheung in Events, Training on Monday, January 23, 2012

Analog Devices will host a webinar titled, The Latest on Driving ADCs Differentially. There are two parts to this online seminar. The first part will take place Wednesday on January 25, 2012, at 12:00 pm EST. It will discuss how to select the right differential ADC driver for your design, and examine basic concepts. The second part of the webcast will take these basic concepts and use them to make the driver selection. The ADI webinar is ideal for all students and engineers who are new to the field, as well as those more experienced engineers looking for a refresher on this or any other part of the signal chain, design, and layout.

ADI Webinar: The Latest on Driving ADCs Differentially »

Introductory to Boundary Scan Workshop

Posted by Ken Cheung in Events, Training on Friday, January 20, 2012

XJTAG will host a free workshop. The event will explain how boundary scan testing can help board designers and engineers. The boundary scan workshop is designed to provide design, development, test, and production engineers with a practical hands-on introduction to boundary scan. Engineers will learn how boundary scan can be used right across the product lifecycle to improve designs, reduce respins and enhance test coverage, fault diagnosis and production yields on complex BGA-populated circuits. The Introductory to Boundary Scan workshop will take place Wednesday, February 29, 2012 at XJTAG’s Cambridge headquarters.

Introductory to Boundary Scan Workshop »

New Cadence Book: Advanced Verification Topics

Posted by Ken Cheung in Research on Thursday, January 19, 2012

Cadence Design Systems published a new book: Advanced Verification Topics. The 229-page book describes the latest techniques and methodologies for verifying today’s most complex IP and systems on chips (SoCs). It discusses topics like metric-driven verification of digital and mixed-signal designs, low-power verification using the UVM, multi-language UVM, and acceleration for the UVM. The Cadence book is ideal for aid verification engineers. It builds on a prior Cadence book, A Practical Guide to Adopting the Universal Verification Methodology (UVM).

New Cadence Book: Advanced Verification Topics »

Making the Most out of Multicore Webinar Series

Posted by Ken Cheung in Events, Training on Wednesday, January 18, 2012

Avnet Electronics Marketing Americas and Freescale Semiconductor are offering a series of webinars. The online seminars will discuss how to make the most of quad core and dual core technologies for next-generation designs. The webcasts are designed for both system architects, and hardware and software engineers. The webinars will demonstrate the best ways to extract the performance potential available from a multicore system, which will enable engineers to design systems that can achieve impressive performance, at a manageable power envelope.

Making the Most out of Multicore Webinar Series »

ADI Webinar: Fundamentals of Clocks and Clocking

Posted by Ken Cheung in Events, Training on Tuesday, January 17, 2012

Analog Devices will host a webinar about the fundamentals of clocks synthesis and distribution. The online seminar will discuss the types of phase-locked loops, the key features of these devices, and the applications they are designed for. The ADI webcast will take place tomorrow (January 18, 2012) at 12:00 pm EST. The webinar is ideal for students and engineers who are new to the field, and also for more experienced engineers looking for a refresher on this or any other part of the signal chain, design, and layout.

ADI Webinar: Fundamentals of Clocks and Clocking »

National Instruments Webinars: Optimize RF Measurements

Posted by Ken Cheung in Events, Training on Monday, January 16, 2012

National Instruments is offering a series of webinars on RF measurements. The webcasts will discuss the fundamentals of making RF measurements and focus on technique, best practices and increasing productivity with the industry’s latest tools. Each of the RF Measurements online seminars will be webcast twice each day, at 10am and 2pm GMT (subtract five hours for eastern standard time). The NI webinars will take place in March. The webcasts will also be available on demand after the series is complete.

National Instruments Webinars: Optimize RF Measurements »

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